750 Palomar Ave, Sunnyvale, CA 94085 | 408-730-2275
My Colfax    

Presentation Slides


Scientific Computing with Intel® Xeon Phi™ Coprocessors

Posted: February 03, 2015

Andrey Vladimirov, Head of HPC Research at Colfax presented: "Scientific Computing with Intel® Xeon Phi™ Coprocessors" at the HPC Advisory Council Stanford Conference 2015.

Click here to learn more


Colfax Developer Boot Camp (1-Day Training) Slides

Posted: October 13, 2014

We are making publicly available the slide deck (277 pages) of the Colfax developer training titled "Parallel Programming and Optimization with Intel Xeon Phi Coprocessors".

This training is an intensive course for developers wishing to leverage the Intel MIC architecture. It is also useful for multi-core processor programming. The course is based on a book of the same name, which contains targeted exercises ("labs") for hands-on practicum.

This year, "Parallel Programming and Optimization..." has visited over 40 locations across the United States: research institutions, government labs, universities, and regional trainings. Over 700 students attended the course. Many of these events were free to attendees thanks to Intel's sponsorship.

Check back with us at the end of the year for a schedule of additional regional trainings, and for the second edition of the book featuring information on future manycore architectures, cluster configuration, networking on Xeon Phi with InfiniBand, usage of the latest compilers and driver stack, computer display-friendly large typeface, and more.

Click here to learn more