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Video: KNL Overview and Hands-on Optimization Demos

Posted: September 29, 2016

Colfax now offers a 2-hour Hands-On Workshop (HOW) video on the best practices for performance optimization for Intel® Xeon Phi™ processor (formerly Knights Landing).

Click here to watch all the 10 episodes


Ninja Developer Platform Based on Intel® Xeon Phi™ Processor

Posted: June 20, 2016

Unleash your code’s potential with the Ninja Developer Platform for Intel® Xeon Phi™ Processor codenamed Knights Landing (KNL). The turnkey Ninja Developer Platform comes fully configured with memory, local storage, CentOS 7.21, Intel tools, and provides how to and optimization guides, and support from Colfax and/or local OEMs.


Machine Learning on Intel® Xeon Phi™ Processors: Image Captioning with NeuralTalk2, Torch

Posted: June 20, 2016

In this demo, we describe a proof-of-concept implementation of a highly optimized machine learning application for Intel Architecture, particularly the Intel Xeon Phi processors (formerly codenamed Knights Landing).


Interview with James Reinders: Future of Intel MIC Architecture, Parallel Programming, Education

Posted: March 06, 2015

During the conversation between James Reinders, the Director and Chief Evangelist at Intel Corporation, and Vadim Karpusenko, Principal HPC Research Engineer at Colfax International, recorded on January 30, 2015 at Colfax International in Sunnyvale, CA, we discussed the future of parallel programming and Intel MIC architecture products: Intel Xeon Phi coprocessors, Knights Landing (KNL), and forthcoming 3rd generation - Knight Hill (KNH). We also talked about how students can learn parallel programming and optimization of high performance applications.


Scientific Computing with Intel® Xeon Phi™ Coprocessors

Posted: February 03, 2015

In this video from the HPC Advisory Council Stanford Conference 2015, Andrey Vladimirov, Head of HPC Research at Colfax presents: Scientific Computing with Intel® Xeon Phi™ Coprocessors


Computational Fluid Dynamics with Fortran on Intel® Xeon Phi™ Coprocessors

Posted: February 03, 2015

Demonstration of Intel Xeon Phi coprocessors accelerating a computational fluid dynamics workload. The application is running on a Colfax SXP8400 workstation.

Learn more and download the Colfax white paper


Heterogeneous Clustering with Homogeneous Code: Asian Options Demo

Posted: January 14, 2014

This demonstration was exhibited by Colfax at SC13 at the Intel corporate booth. It shows how one can use Intel® Xeon Phi™ coprocessors in a computing cluster without modifying a single line of code in an application designed for general-purpose multicore CPUs. Our new white paper describes the network configuration necessary for such heterogeneous clustering and analyzes the applicability range and the limitations of this approach.

Learn more and download the Colfax white paper


Test-driving Intel® Xeon Phi™™ Coprocessors with a Basic N-body Simulation

Posted: January 07, 2013

The visualization shown below demonstrates the results and the performance of the N-body simulation on Intel® Xeon® processors and Intel® Xeon Phi™™ coprocessors. The code running the visualization has the same force calculation algorithm as the code presented in this Colfax white paper